Hereinafter, there is briefly explained a memory cell access procedure of a general dynamic random access memory (DRAM).
At first, if an active command and a row address are inputted to the DRAM, data of memory cells connected to a word line actuated by the row address are coupled to pairs of bit lines, wherein there occurs a minute voltage difference between two corresponding bit lines according to the data stored in the memory cells. The minute voltage difference of the data fed to each pair of bit lines is sense-amplified by a bit line sense amplifier and the data become to have voltage levels which are logically detectable. Then, if a column address is inputted to the DRAM together with a read or write command, data of a certain memory cell amplified by the bit line sense amplifier, which corresponds to a bit line selected by a column selection signal corresponding to the column address, is outputted or an inputted external data is written on a pair of bit lines selected by the column selection signal. After then, the pair of bit lines is precharged in response to a precharge command and initialized so as to respond to a next active command.
Meanwhile, in the above procedure, tRAS represents a time until a next read or write command is inputted after an active command is coupled to the DRAM. A minimum time from the active command inputted to the read or the write command coupled to the DRAM is represented as tRASmin. The tRASmin is a minimum time required for the bit line sense amplifiers detecting memory cell data of a selected word line and it should be secured to prevent the memory cell data from being lost.
FIG. 1 is a block diagram of a conventional semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device includes an active driving block 10 and a precharge signal generating block 20.
The active driving block 10 contains an active signal generating unit 12 for producing an active signal ratvp10 and an internal active signal ratvpz11 based on a refresh-active signal intaxp8 and an external active signal extaxp8 provided from the outside, and an active region detecting unit 14 for detecting an active region from the activation of the active signal ratvp10 to that of a feedback precharge signal rpcgzp11.
The precharge signal generating block 20 has an external precharge detecting unit 22 for detecting an external precharge signal pcgp6, and a pulse adjusting unit 24 for outputting an internal precharge signal rpcgpz11 in response to the actuation of an output signal pcg of the external precharge detecting unit 22 and internally generated precharge signals apcg and sadly.
For the reference, the refresh-active signal intaxp8 is an active command actuated when performing auto-refresh and self-refresh operations. As internally generated precharge signals, there are the auto-precharge signal apcg and the refresh-precharge signal sadly. The auto-precharge signal apcg is activated after an auto-precharge command is inputted and the tRASmin is passed. The refresh-precharge signal sadly is actuated after a refresh command is inputted and the tRASmin is passed.
FIG. 2A provides a circuit diagram of the external precharge detecting unit 22 in FIG. 1.
Referring to FIG. 2A, the external precharge detecting unit 22 contains NMOS transistors NM2 and NM3 connected in parallel to each other whose gates are coupled with a bank driving signal eat_bk and a bank precharge signal eat<10>, respectively, a PMOS transistor PM1 whose gate is inputted with the external precharge signal pcgp6 and whose source and drain are connected to a supply voltage node and an output node, respectively, an NMOS transistor NM1 whose gate is coupled with the external precharge signal pcgp6 and whose drain and source are attached to the output node and a drain of the NMOS transistor NM2, respectively, a NAND gate ND1 which receives a power-up signal pwrup and a signal on the output node to thereby output the precharge signal pcg, and a PMOS transistor PM2 whose gate is coupled with the output signal pcg of the NAND gate ND1 and whose source and drain are connected to the supply voltage node and a drain of the NMOS transistor NM1, respectively.
FIG. 2B describes a circuit diagram of the pulse adjusting unit 24 in FIG. 1.
Referring to FIG. 2B, the pulse adjusting unit 24 contains a NOR gate NR1 receiving the auto-precharge signal apcg, the refresh-precharge signal sadly and the precharge signal pcg, a flip-flop 24a receiving an output signal of the NOR gate NR1 as a set signal and the feedback refresh signal rpcgzp11 as a reset signal, an inverter I1 for inverting an output signal of the flip-flop 24a to thereby output the internal precharge signal rpcgpz11, and an inverter chain 24b for delaying an output signal of the inverter I1 to thereby output the feedback precharge signal rpcgzp11.
FIG. 3 represents a waveform diagram showing an operation of the memory device in FIG. 1, wherein the external precharge signal pcgp6 is inputted before the tRASmin is passed.
Referring to FIG. 3, the bank driving signal eat_bk is activated at first and, then, the internal active signal ratvpz11 is actuated by the active signal generating unit 12 in response to the external active signal extaxp8. After then, if the external precharge signal pcgp6 is inputted thereto, the external precharge detecting unit 22 detects the external precharge signal pcgp6 and the pulse adjusting unit 24 outputs the internal precharge signal rpcgpz11 by using the output signal pcg of the external precharge detecting unit 22.
In the meantime, as mentioned above, if the external precharge signal pcgp6 is inputted before the tRASmin is passed after the external active signal extaxp8 inputted, the memory cell data are lost. In order to detect and amplify the memory cell data of the selected word line after the external active signal extaxp8 is inputted and to secure the cell data stably, the tRASmin should be secured. Therefore, if the external precharge signal pcgp6 is inputted before the tRASmin is passed, the bit line precharge operation starts before the memory cell data of the selected word line are stably secured. As a result, the memory cell data are lost.
The above problem occurs when the external precharge signal is inputted before the tRASmin is passed. This problem does not happen by the auto-precharge signal apcg and the refresh-precharge signal sadly because these signals are internally generated after the tRASmin is passed. On the other hand, this may occur by the external precharge signal pcgp6 because the external precharge signal pcgp6 is provided to the memory device from the outside by a user.